Synopsys contractor/Intern in FPGA synthesis and Freshers

1. Looking for M.Tech/M.E. VLSI candidates with exposure to Python scripting to work as contractor/Intern in FPGA synthesis team at Synopsys.

Required skills: Python scripting Digital design RTL (Verilog, VHDL, System Verilog) If you are interested, please share your resume at Kiran.Bhise@synopsys.com

* Send ASAP.



2. Here's a fresh new opportunity for package substrate design in Canada!
Come work with a great team and culture on advanced package substrate design for high end IP/PHY/circuit - share the passion!

https://www.linkedin.com/posts/luis-sim%C3%B5es-a4944711_package-design-engineer-synopsys-activity-6866741950054203392-JHic

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