Capgemini is Hiring Synthesis, Physical Design, Physical verification, and STA

 Capgemini are looking for Synthesis, Physical Design, Physical verification, and STA Engineers to work in Soc turnkey/ODC's projects. Kindly share resumes to 

catharine.reshma@capgemini.com

Comments

Post a Comment

Popular posts from this blog

Intel is Hiring Pre Silicon Verification Engineer

an experienced Pre Silicon Verification Engineer. Please find the desired qualification below. Kindly DM me if you are looking forward to an exciting job role with Intel Basic Qualifications: 8-15yrs of relevant experience Hands-on RTL debug expertise using VCS/Verdi toolchain Experience with OVM/UVM testbench methodology and writing of tests Good scripting skills to analyze IP logs and transaction-level debugging Preferred Qualifications: Experienced in PCIe link training and protocols Knowledge of CXL and cache coherency protocols Excellent communication skills and working in a team environment for integration and debug https://www.linkedin.com/in/avinash-k-v-5a0309100/
Read more

Samsung Semiconductors India R&D, Bangalore!! Hiring

  Samsung Semiconductors India R&D, Bangalore!! Hiring PDK LVS Engineers with 4+ years of experience. If interested please share your resume to  k.swetha@samsung.com Location : Bangalore Job responsibilities: Should have in depth knowledge of a technology node with respect to understanding the aspects of technology like BEOL FEOL stacks, Understanding the design rules, Device offering in a technology, Device structures, Working of devices, variants of the devices, differences in device variants with respect to working and construction Should have good understanding of CMOS fundamentals and Circuit Design Concepts Should have in depth knowledge of running the physical verification tools like DRC/LVS/ERC/PERC etc Should have experience in physical verification (DRC, LVS, ERC, PERC) rulefile QA/Development with ICV/Calibre/PVS Should have experience in running regression based test suites for Quality analysis of phsical verification rulefiles. Should have proficiency in progr...
Read more

TESSOLVE Is Hiring CDC/Lint

  TESSOLVE Is Hiring CDC/Lint Exp: 4-8 years; Qualification BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS Experience 4 to 8 years No of Position 4 Location Bangalore Requirements Synthesis Constraints development, LINT checks, CDC checks. Working / leading full-chip STA closure, defining mode requirements & corners for timing closure. Formal Verification-Synopsys Formality/ Cadence. CTS & ECO cycle. JOB FUNCTION: IT Hardware : Hardware Products & Services INDUSTRY: Telecom, IT-Hardware/Networking SPECIALIZATION: Hardware Design QUALIFICATION: BE/ B.Tech (Engineering) EMPLOYMENT TYPE: Full Time
Read more