ATRIA LOGIC Hiring for VLSI Design & Verification

 Trained candidates are preferable

#Eligibility : M-Tech(2018,19,20 & 21), B-Tech(2017,2018 & 2019) #Verilog #Systemverilog #UVM 1.As a Verification engineer Working on full chip Verification and UVM Methodology. 2. System Verilog is a must. 3. Worked on passing test cases, test benches, Building environment. Good knowledge of Functional coverage, Code Coverage, Assertions, Constraints 3. Good communication skills. Basic hashtag #knowledge on protocols like AXI, AHB, APB etc. #pleaseshare your resume to atrialogic11@gmail.com

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