Careers In VLSI

  Mediatek is hiring for the following positions. https://www.linkedin.com/feed/update/urn:li:activity:6871399203931869184/ 5-15 Years : Memory Design Engineers, Verification Engineers(SOC/ PCIe/USB/Serdes) , RTL Design (Modem Processor) , DFT Engineers(ATPG/MBIST) 3-15 Years : L1, L2, L3, L4 Protocol Stack Engineers, DSP Engineers

  Qualcomm is looking for Synthesis / STA / Constraints skillset for Bangalore / Hyderabad Location with 6+ yrs exp. Intrested folks can share updated resume to  veenb@qti.qualcomm.com .

  Samsung Semiconductors India R&D, Bangalore!! Hiring PDK LVS Engineers with 4+ years of experience. If interested please share your resume to  k.swetha@samsung.com Location : Bangalore Job responsibilities: Should have in depth knowledge of a technology node with respect to understanding the aspects of technology like BEOL FEOL stacks, Understanding the design rules, Device offering in a technology, Device structures, Working of devices, variants of the devices, differences in device variants with respect to working and construction Should have good understanding of CMOS fundamentals and Circuit Design Concepts Should have in depth knowledge of running the physical verification tools like DRC/LVS/ERC/PERC etc Should have experience in physical verification (DRC, LVS, ERC, PERC) rulefile QA/Development with ICV/Calibre/PVS Should have experience in running regression based test suites for Quality analysis of phsical verification rulefiles. Should have proficiency in programming la

  Cadence Design Systems is looking for Intern- Technical Writer - Noida Education : BTech/MTech/BSc/MSc Criteria : 2021 pass out with 70% or 7 CGPA Work Location : Noida Pay : 2,64,000 - 3,00,000 Job Description : We are looking for fresh college graduates to work as interns in our team. Candidates should have keen interest in electronics and should demonstrate excellent communication skills. As a part of your job, you will be required to understand electronic engineering concepts and then apply that knowledge to create end-user content. As an intern, you will: ·      Work under the technical writing team members and learn about technical writing fundamentals and Cadence documentation standards. ·      Work with cross-function teams to gain an understanding of assigned Cadence products.  ·      Assist the team in proofreading & performing language reviews of the user manuals, blogs, videos, and more.  ·      Revise and validate technical documents against the software versions, of

 Y ou will be part of  #Design  Enablement focused on pathfinding and development of  #advanced  memory technology and  #circuits  to enable best-in-class  #memory  collateral/ #IP  and  #product  design. Exp: 3-5 yrs. Notice Period: 30 days. Please share your resume to  jayanth1053@Cientra.com

  Job Location: Bangalore Notice Period: 15 to 30 days •            4-7 years of experience in ASIC Physical Design •            Have good knowledge of entire physical design process from floorplan till GDS generation •            Good Exposure to Physical Verification Process •            Have hands-on experience in latest sub-micron technologies below 10 nm •            Hands –on experience in leading PnR tools Synopsys ICC/ICC2 •                    Experience in low power designs and handling congestion or timing critical tiles will be preferred •            Should be a quick learner and have good attention to detail •            Experience in ECO implementation preferred •            Scripting skills in Perl/Tcl/Python etc •            Must have good communication & problem-solving skills. •            Should be able to handle PnR tasks with minimal supervision share your resume to  rajeshbabu.p@acldigital.com

  SkandySys is hiring DFT Engineers with 3+ years of experience. It's really a very good opportunity for experienced peoples. Interested people's can share your resumes to  girish.k@skandysys.com

an experienced Pre Silicon Verification Engineer. Please find the desired qualification below. Kindly DM me if you are looking forward to an exciting job role with Intel Basic Qualifications: 8-15yrs of relevant experience Hands-on RTL debug expertise using VCS/Verdi toolchain Experience with OVM/UVM testbench methodology and writing of tests Good scripting skills to analyze IP logs and transaction-level debugging Preferred Qualifications: Experienced in PCIe link training and protocols Knowledge of CXL and cache coherency protocols Excellent communication skills and working in a team environment for integration and debug https://www.linkedin.com/in/avinash-k-v-5a0309100/

  Looking for Immediate joiners with Expertise on Physical Design/RTL Design / DFT Engineers/ STA Engineers with 3+ Years of experience . SHARE / REFER to  priyanka.s@sevitechsystems.com

 ACL  hiring for the Multiple positions, 1) Physical Design 2) Physical Verification 3) ASIC/IP/SOC verification engineer 4) FPGA RTL designers 5) Validation Experience - 3+ years Job location - Bangalore/Hyderabad Interested candidates please share your updated CV at  manjula.k@acldigital.com